TSMC releases roadmap that takes us beyond the 3nm process node

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The largest foundry in the world belongs to the Taiwanese TSMC. This is the company that turns Apple’s chip designs into real chips like the A15 Bionic (which powers the iPhone 13 series and has 15 billion transistors in each chip). TSMC is also responsible for the M1 chip line, including the M1 Ultra, powered by its 114 billion transistors. The M1 Ultra was created by combining two M1 Max chips.

Earlier this week, TSMC’s 2022 Technology Symposium kicked off, including the release of a roadmap by TSMC for its advanced process nodes with 3nm (N3) and 2nm (N2) chips. The smaller the process node, the fewer transistors are used in a chip. And that is important, because traditionally, the higher the number of transistors, the more powerful and energy-efficient a chip is.

The next major process node is 3nm, which Apple hopes to use on next year’s iPhone 15 series. TSMC expects to have five N3 nodes in the next three years. Instead of releasing a new node every two years, which was common for the foundry and industry, TSMC will now introduce a new node every two and a half years, increasing to every three years with the N2 (2nm) process node . This data is known as the node launch cadence.

TSMC will continue to use FinFET field effect transistors for its 3nm process node, while Samsung will debut its gate all-round transistors with its 3nm chips). On the other hand, TSMC won’t start using gate all-round transistors until it starts shipping its 2nm chips. TSMC is quickly letting its more advanced customers with chip designs demand N2 when it becomes available, while the foundry’s less technically demanding customers will likely decide to stick with a 3nm process node for years to come.

The foundry’s first 3nm node to ship will begin high volume production in the second half of this year. Deliveries of 3nm chips will take place in early 2023. According to AnandTechN3 is made for early adopters, including: Apple that could benefit from the increase in performance, power and area (PPA) provided by leading nodes.

The N3E node reduces power consumption by 34% or delivers a performance bump of 18%. By 2024, the foundry expects to offer its N3P node that focuses on performance improvements. And N3S is the density oriented version of the 3nm node. Density tells us how many million transistors fit in a square mm of space. High-density chips allow more circuits to be placed on a chip while delivering a higher operating speed.

The 3nm process nodes are the latest from TSMC to provide the FinFET transistor based process nodes. These transistors use a “fin” design from which they get their name. TSMC will introduce its 2nm process node technology in 2025.

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